The use of semiconductor technology has, over the last few decades, revolutionized the use of electrical and electronic goods. In particular, the increased use of semiconductor technology has resulted from an unappeasable need by business (as well as individuals) for better, smaller, faster and more reliable electronic goods.
The semiconductor manufacturers have therefore needed to make commensurate improvements in product quality, as well as in the speed, quality and reliability of the semiconductor manufacturing process. Clearly, in the mass-manufacture of semiconductors, the manufacturer needs to minimize the number of faulty semiconductors that are manufactured. Furthermore, the manufacturer clearly needs to recognize, as early as possible in the manufacturing process, when faulty semiconductors are being manufactured, so that the manufacturing process can be checked and, if appropriate, corrected.
A semiconductor wafer typically includes multi-layer integrated circuits (ICs) that include multiple oxide (insulating) layers and metal (conducting) layers. Horizontal layers are connected to each other by vertical contacts (connecting the first metal layer to the substrate and additional layers that include the transistors themselves) or by vertical vias (connecting conductors of two distinct metal layers). As each metal layer is separated from another layer by an oxide layer (that may also include conductive patterns) the vias/contacts are generated by three steps:                (i) Drilling vertical holes through the oxide layer,        (ii) Performing metal deposition that results in filling the vias/contacts but also results in residue metal, and        (iii) Polishing the oxide layer such that the residue metal disappears.        
Many ICs have multiple metal layers, thus the three-step via/contact generation process is repeated many times.
By continuously inspecting semiconductor wafers throughout the manufacturing process, flawed wafers may be removed and, if appropriate, the wafer or wafer manufacturing process corrected at any of the various steps. A wafer inspection may therefore occur after each via/contact generation process. This is much more preferable than completing the whole wafer manufacturing process, only to find that a defect in a wafer, an IC, a via or a layer exists in a final inspection, or by failure during use.
In the field of this invention, the use of automatic defect characterization (ADC) is known in wafer inspection techniques. U.S. Pat. No. 5,808,735 by Lee et al. describes a method for detecting and characterizing defects on a test surface of a semiconductor wafer using a pixel comparison technique between a specially prepared reference blank wafer, and the blank wafers.
European patent application EP 0869352A, from the same applicant as the present invention, describes a further technique for detecting metallic contaminants in a sub-micron semiconductor wafer by comparing a reference (pre-annealed) wafer with an annealed wafer. Such an inspection technique teaches the comparison of a pre-process (reference) wafer with a post-process wafer to determine particle defects, metallic contaminants etc. introduced during the process. A further example of a reference wafer technique, as commonly employed in the field of wafer inspection, is described in U.S. Pat. No. 5,870,187 by Uritsky et al., whereby wafer scanning is used to (i) align wafer surface scan maps, and (ii) locating particle contamination defects, for comparison purposes between a ‘before’ and ‘after’ wafer handling or processing operation.
As previously indicated, after the manufacturing process, particularly in the production of ultra-high density integrated circuits, chemical-mechanical polishing (CMP) processes are used to remove material from the surfaces of wafers. CMP processes typically remove either conductive materials or insulative materials from the surface of the wafer to produce a flat, uniform surface upon which, if desired, additional layers of devices may be fabricated.
In a typical CMP process, a wafer is pressed against a polishing pad in the presence of slurry under controlled chemical pressure, velocity, and temperature conditions. The slurry solution typically contains small abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer.
The polishing pad is generally a planar pad made from a continuous phase matrix material, such as polyurethane. Thus, when the pad and/or the wafer moves with respect to the other, material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and/or by the chemical (chemical removal) in the slurry.
When a conductive layer is polished from a wafer, the CMP processes must accurately stop polishing the wafer at a desired endpoint. Conductive layers are typically deposited over insulative layers to fill vias or trenches in the insulative layer and to form electrical interconnections between device features on the wafer.
If the CMP process is stopped before the desired endpoint, leading to “under-polishing” of the wafer as it is termed in the art, then any interconnects will not be electrically isolated from one another and shorting may well occur in the circuit. Conversely, if the CMP process is stopped after the desired endpoint, leading to “over-polishing” as it is termed in the art, then interconnects may be completely removed from the wafer. Therefore, to avoid serious defects in a wafer, it is critical that the CMP process is accurately controlled and stopped at the desired endpoint.
It is particularly difficult to determine the endpoint of the CMP process on wafers that have small “critical areas”. The critical areas are typically depressions on the surface of the wafer that are the last point on the wafer from which the conductive material is removed by CMP processing.
In the case of metal CMP, which includes tungsten and/or copper metalization of the wafer, the factors contributing to the incomplete removal of the metal range from the incoming metal thickness variation, through the age of the polish consumables, to equipment issues such as interruption in slurry flow or malfunction of the endpoint hardware. The high costs associated with 300 mm manufacturing necessitate a tight control of the metal CMP process in order to minimize the occurrence of residual metal. Residual metal, caused by an incomplete CMP process, adversely impacts the overall product cycle time and, consequently, the production costs.
The inspection of metalized layers has been predominantly left to human visual inspection, in conjunction with microscopic equipment or using laser light-based inspection tools. The visual inspection process is primarily focused to identify if there is any residue metal left on the post CMP wafer. It is known that this stage is a very important review stage in any production environment, as a small amount of residue metal left on the wafer will damage an entire die and lead to a poor yield.
This human visual inspection process is renowned for being inaccurate due to various factors including stress, eye fatigue and boredom of the operator. Complete inspection of the entire polished wafer surface is not possible. Furthermore, it is prone to human judgment and therefore prone to the inconsistencies between different perceptions by different operators as to the significance of a finding. In addition, smaller circuit geometry and higher throughput requirements are exceeding the feasibility of using a microscope for inspection of residual metal for advanced technology nodes. This situation is further complicated in the case of 300 mm wafers, where there is greater than two-fold increase in the inspection surface area compared to a 200 mm wafer. All of which further results in operator stress, eye fatigue, and often lower quality inspection.
A known post-CMP visual inspection process 100, as shown in FIG. 1, involves the stages:
(i) Inspection with naked eye 120 after CMP step 110.
(ii) Review the wafer using, for example, a microscope 140. A reviewer may give feedback on the quality of the wafer, obtained using the microscope, or recommendations to the CMP team. A human decision is then made on the wafer, and if appropriate, the wafer may be returned to the CMP tool for re-polishing if it is deemed “under-polished”, or the wafer rejected. Otherwise the polished wafer is passed to the next process stage 150.
The above inspection approach has the significant disadvantage that the process is very time consuming. In addition, the inspection tool used to determine whether any defect exists fails to provide a quantitative measure of the residue metal on the wafer.
A yet further significant disadvantage emanates from there being a delayed feedback of information to the CMP tool, via the Operator.
Thus, there exists a need in the field of the present invention to provide an improved method and apparatus for a post-CMP residual metal inspection process.